1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to methods of placement and routing for an integrated circuit design.
2. Description of Related Art
An important phase in the design of an integrated circuit is to verify that each logic path in the integrated circuit design meets all timing constraints required to meet performance specifications. The verification of the timing for each logic path in an integrated circuit design is typically called timing closure. For example, if the propagation delay is too long in a path that propagates a clock signal to a flip-flop, the flip-flop may not be set to the correct value when the clock signal arrives, resulting in a timing violation. Also, signal routing congestion may occur in locations where there are more signals to route than there is available routing area on the chip. The locations in the integrated circuit design where timing violations or congested routing areas occur are referred to herein as critical areas.
Timing closure is a resource-intensive task in which all timing violations and congested signal routes in the placement and routing must be resolved before an integrated circuit design may be taped out, that is, generated in mask form for depositing and etching layers of various materials on a silicon substrate. Place and route tools typically resolve timing and signal congestion problems in critical areas by moving the problems outside of the critical areas into the surrounding logic.